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clk

clock_source v9.1

Parameters clockFrequency 50000000 clockFrequencyKnown true inputClockFrequency 0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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CPU

altera_nios2 v9.1

Parameters userDefinedSettings setting_showUnpublishedSettings false setting_showInternalSettings false setting_shadowRegisterSets 0 setting_preciseSlaveAccessErrorException false setting_preciseIllegalMemAccessException false setting_preciseDivisionErrorException false setting_performanceCounter false setting_perfCounterWidth _32 setting_interruptControllerType Internal setting_illegalMemAccessDetection false setting_illegalInstructionsTrap false setting_fullWaveformSignals false setting_extraExceptionInfo false setting_exportPCB false setting_debugSimGen false setting_clearXBitsLDNonBypass true setting_branchPredictionType Static setting_bit31BypassDCache true setting_bigEndian false setting_bhtPtrSz _8 setting_bhtIndexPcOnly false setting_avalonDebugPortPresent false setting_alwaysEncrypt true setting_allowFullAddressRange false setting_activateTrace true setting_activateTestEndChecker false setting_activateMonitors true setting_activateModelChecker false setting_HDLSimCachesCleared true setting_HBreakTest false resetSlave SDRAM.s1 resetOffset 0 muldiv_multiplierType EmbeddedMulFast muldiv_divider true mpu_useLimit false mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mpu_minInstRegionSize _12 mpu_minDataRegionSize _12 mpu_enabled false mmu_uitlbNumEntries _4 mmu_udtlbNumEntries _6 mmu_tlbPtrSz _7 mmu_tlbNumWays _16 mmu_processIDNumBits _10 mmu_enabled false mmu_autoAssignTlbPtrSz true mmu_TLBMissExcSlave mmu_TLBMissExcOffset 0 manuallyAssignCpuID false impl Small icache_size _4096 icache_ramBlockType Automatic icache_numTCIM _0 icache_burstType None exceptionSlave SDRAM.s1 exceptionOffset 32 debug_triggerArming true debug_level Level2 debug_jtagInstanceID 0 debug_embeddedPLL true debug_debugReqSignals false debug_assignJtagInstanceID false debug_OCIOnchipTrace _128 dcache_size _2048 dcache_ramBlockType Automatic dcache_omitDataMaster false dcache_numTCDM _0 dcache_lineSize _4 dcache_bursts false cpuReset false cpuID 0 clockFrequency 50000000 breakSlave CPU.jtag_debug_module breakOffset 32 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments CPU_IMPLEMENTATION "small" BIG_ENDIAN 0 CPU_FREQ 50000000u ICACHE_LINE_SIZE 32 ICACHE_LINE_SIZE_LOG2 5 ICACHE_SIZE 4096 DCACHE_LINE_SIZE 0 DCACHE_LINE_SIZE_LOG2 0 DCACHE_SIZE 0 FLUSHDA_SUPPORTED HAS_JMPI_INSTRUCTION EXCEPTION_ADDR 0x20 RESET_ADDR 0x0 BREAK_ADDR 0xa000020 HAS_DEBUG_STUB HAS_DEBUG_CORE 1 CPU_ID_SIZE 1 CPU_ID_VALUE 0x0 HARDWARE_DIVIDE_PRESENT 1 HARDWARE_MULTIPLY_PRESENT 1 HARDWARE_MULX_PRESENT 0 INST_ADDR_WIDTH 28 DATA_ADDR_WIDTH 29

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JTAG_UART

altera_avalon_jtag_uart v9.1

Parameters allowMultipleConnections false hubInstanceID 0 readBufferDepth 64 readIRQThreshold 8 simInputCharacterStream simInteractiveOptions INTERACTIVE_ASCII_OUTPUT useRegistersForReadBuffer false useRegistersForWriteBuffer false useRelativePathForSimFile false writeBufferDepth 64 writeIRQThreshold 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments WRITE_DEPTH 64 READ_DEPTH 64 WRITE_THRESHOLD 8 READ_THRESHOLD 8

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Interval_Timer

altera_avalon_timer v9.1

Parameters alwaysRun false counterSize 32 fixedPeriod false period 125.0 periodUnits MSEC resetOutput false snapshot true systemFrequency 50000000 timeoutPulseOutput false timerPreset CUSTOM deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ALWAYS_RUN 0 FIXED_PERIOD 0 SNAPSHOT 1 PERIOD 125.0 PERIOD_UNITS "ms" RESET_OUTPUT 0 TIMEOUT_PULSE_OUTPUT 0 FREQ 50000000u LOAD_VALUE 6249999ULL COUNTER_SIZE 32 MULT 0.0010 TICKS_PER_SEC 8u

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sysid

altera_avalon_sysid v9.1

Parameters id 845204719 timestamp 1297033579 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments ID 845204719u TIMESTAMP 1297033579u

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SDRAM

altera_avalon_new_sdram_controller v9.1

Parameters TAC 5.5 TMRD 3 TRCD 20.0 TRFC 70.0 TRP 20.0 TWR 14.0 casLatency 3 clockRate 50000000 columnWidth 8 dataWidth 16 generateSimulationModel false initNOPDelay 0.0 initRefreshCommands 2 masteredTristateBridgeSlave model custom numberOfBanks 4 numberOfChipSelects 1 pinsSharedViaTriState false powerUpDelay 100.0 refreshPeriod 15.625 registerDataIn true rowWidth 12 size 8388608 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments REGISTER_DATA_IN 1 SIM_MODEL_BASE 0 SDRAM_DATA_WIDTH 16 SDRAM_ADDR_WIDTH 22 SDRAM_ROW_WIDTH 12 SDRAM_COL_WIDTH 8 SDRAM_NUM_CHIPSELECTS 1 SDRAM_NUM_BANKS 4 REFRESH_PERIOD 15.625 POWERUP_DELAY 100.0 CAS_LATENCY 3 T_RFC 70.0 T_RP 20.0 T_MRD 3 T_RCD 20.0 T_AC 5.5 T_WR 14.0 INIT_REFRESH_COMMANDS 2 INIT_NOP_DELAY 0.0 SHARED_DATA 0 STARVATION_INDICATOR 0 TRISTATE_BRIDGE_SLAVE "" IS_INITIALIZED 1 SDRAM_BANK_WIDTH 2 CONTENTS_INFO ""

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Red_LEDs

altera_up_avalon_parallel_port v9.1

Parameters board DE1 custom_port false preset LEDs leds Red sevensegs 3 to 0 gpio GPIO 0 (JP1) DW 10 direction Output only custom_DW 32 custom_direction Input only capture false edge Rising irq false irq_type Level AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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Green_LEDs

altera_up_avalon_parallel_port v9.1

Parameters board DE1 custom_port false preset LEDs leds Green sevensegs 3 to 0 gpio GPIO 0 (JP1) DW 8 direction Output only custom_DW 32 custom_direction Input only capture false edge Rising irq false irq_type Level AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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HEX3_HEX0

altera_up_avalon_parallel_port v9.1

Parameters board DE1 custom_port false preset Seven Segment Displays leds Green sevensegs 3 to 0 gpio GPIO 0 (JP1) DW 32 direction Output only custom_DW 32 custom_direction Input only capture false edge Rising irq false irq_type Level AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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Slider_Switches

altera_up_avalon_parallel_port v9.1

Parameters board DE1 custom_port false preset Slider Switches leds Green sevensegs 3 to 0 gpio GPIO 0 (JP1) DW 10 direction Input only custom_DW 32 custom_direction Input only capture false edge Rising irq false irq_type Level AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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Pushbuttons

altera_up_avalon_parallel_port v9.1

Parameters board DE1 custom_port false preset Pushbuttons leds Green sevensegs 3 to 0 gpio GPIO 0 (JP1) DW 4 direction Input only custom_DW 32 custom_direction Input only capture true edge Falling irq true irq_type Edge AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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Expansion_JP1

altera_up_avalon_parallel_port v9.1

Parameters board DE1 custom_port false preset Expansion Header leds Green sevensegs 3 to 0 gpio GPIO 0 (JP1) DW 32 direction Bidirectional (tri-state) custom_DW 32 custom_direction Input only capture true edge Falling irq true irq_type Edge AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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Expansion_JP2

altera_up_avalon_parallel_port v9.1

Parameters board DE1 custom_port false preset Expansion Header leds Green sevensegs 3 to 0 gpio GPIO 1 (JP2) DW 32 direction Bidirectional (tri-state) custom_DW 32 custom_direction Input only capture true edge Falling irq true irq_type Edge AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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Serial_Port

altera_up_avalon_rs232 v9.1

Parameters baud 115200 parity Odd data_bits 8 stop_bits 1 AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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AV_Config

altera_up_avalon_audio_and_video_config v9.1

Parameters device On-Board Peripherals board DE1 eai true audio_in Microphone to ADC dac_enable true mic_bypass false line_in_bypass true mic_attenuation -6dB data_format Left Justified bit_length 32 sampling_rate 48 kHz bosr 250fs/256fs sr_register 0 video_format NTSC AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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Audio

altera_up_avalon_audio v9.1

Parameters audio_in true audio_out true dw 32 AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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PS2_Port

altera_up_avalon_ps2 v9.1

Parameters AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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SRAM

altera_up_avalon_sram v9.1

Parameters board DE1 pixel_buffer false AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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VGA_Pixel_Buffer

altera_up_avalon_video_pixel_buffer_dma v9.1

Parameters addr_mode X-Y start_address 134217728 back_start_address 134217728 image_width 320 image_height 240 color_space 16-bit RGB AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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VGA_Pixel_RGB_Resampler

altera_up_avalon_video_rgb_resampler v9.1

Parameters input_type 16-bit RGB output_type 30-bit RGB alpha 255 input_bits 16 input_planes 1 output_bits 10 output_planes 3 AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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VGA_Pixel_Scaler

altera_up_avalon_video_scaler v9.1

Parameters width_scaling 2 height_scaling 2 width_in 320 height_in 240 width_out 640 height_out 480 color_bits 10 color_planes 3 AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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VGA_Char_Buffer

altera_up_avalon_video_character_buffer_with_dma v9.1

Parameters vga_device On-board VGA DAC enable_transparency true color_bits 1-bit resolution 80 x 60 AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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VGA_Dual_Clock_FIFO

altera_up_avalon_video_dual_clock_buffer v9.1

Parameters color_bits 10 color_planes 3 AUTO_CLOCK_STREAM_IN_CLOCK_RATE 50000000 AUTO_CLOCK_STREAM_OUT_CLOCK_RATE 25000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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VGA_Controller

altera_up_avalon_video_vga_controller v9.1

Parameters board DE1 device VGA Connector underflow_flag false AUTO_CLOCK_RESET_CLOCK_RATE 25000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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CPU_fpoint

altera_nios_custom_instr_floating_point v6.1

Parameters useDivider true deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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clk_27

clock_source v9.1

Parameters clockFrequency 27000000 clockFrequencyKnown true inputClockFrequency 0 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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External_Clocks

altera_up_avalon_clocks v9.2

Parameters board DE1 sys_clk_freq 50 sdram_clk true vga_clk true audio_clk true audio_clk_freq 12.288 AUTO_CLK_IN_PRIMARY_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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Alpha_Blending

altera_up_avalon_video_alpha_blender v9.1

Parameters mode Simple AUTO_CLOCK_RESET_CLOCK_RATE 50000000 AUTO_DEVICE_FAMILY Cyclone II deviceFamily Cyclone II generateLegacySim false

  

Software Assignments (none)

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Counter

simple_counter v1.0

Parameters deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)