UNIVERSITY OF BRITISH COLUMBIA

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

 

EECE 476: Computer Architecture

Fall 2005

Assignment 2: Single-cycle vs Multi-cycle CPU Design

Quiz Date:  Thursday, October 6, 2005

 

NOTE:  Homework problems are for practice before the quiz. Do not hand them in.

 

Objective

Practice designing parts of a CPU datapath and controller. This design work reinforces your understanding of the datapath operation and control sequences. Compare the performance of a single-cycle and multi-cycle CPU.

Problems

SINGLE-CYCLE DATAPATH DESIGN

1.      What changes are needed to add the J, JR, JAL, and LUI instructions to the MIPS datapath?  Start with the datapath diagram on slide 12 of lecture 7.

a.       The JR instruction is an R-type that jumps to the 32-bit value taken from register rs, ie PC ß REGFILE[rs]. What should be done with the lowest two bits?

b.      The JAL instruction is a J-type that works just like the J instruction. However, it is used for a procedure call, so the “return” address (PC+4) must be saved by writing it into register $31 ($ra), ie:

                         REGFILE[31] ß PC+4; PC ç {PC[31:28],Imm26,2b’0}.

c.       The LUI instruction is an I-type. It was discussed in lecture.

2.      There are some remaining instructions listed under Core Instruction Set in the textbook green card. Does your datapath support all of these instructions? If not, what instructions need further changes? The remaining instructions are: ADDI, ADDIU, ADDU, AND, ANDI, BNE, NOR, OR, ORI, SLT, SLTI, SLTIU, SLTU, SLL, SRL, SUB, SUBU. Note that we will not consider the byte and halfword instructions: LBU, LHU, SB, SH.

MULTI-CYCLE DATAPATH DESIGN

3.      Repeat question 1 using the multi-cycle MIPS datapath on slide 3 of lecture 10.


CONTROLLER DESIGN

4.      For the single-cycle MIPS datapath, determine the control signal values needed to implement the J, JR, JAL, and LUI instructions in question 1. Give these values in the form of a table where you show both the expected input (opcode) and desired output (control signals) for each instruction. Can any of the control signals be assigned a don’t care ‘X’ value?

5.      For the multi-cycle MIPS datapath, what is the RTL sequence needed to execute a J instruction?  How many cycles does it take?  If you wanted it to take 1 fewer cycles, what changes are necessary to the datapath + controller?

6.      For the multi-cycle MIPS datapath, what is the RTL sequence needed to execute a SW instruction?  How many cycles does it take?

PERFORMANCE AND BENCHMARKING

7.      What are the 2 fundamental concepts in the performance measurement of CPUs? Which one is most important for this course? Give two examples of a “performance metric” for each of these concepts.

8.      Explain what is wrong with each of the following performance metrics:

a.       Instructions per second,

b.      Clock speed, and

c.       Cycles per instruction.

9.      Using the performance equation, determine which is faster, CPU X or Y, for each of the two programs, A and B, below.

a.       Program A has 46% arithmetic, 20% load, 24% branch, 10% store instructions.

b.      Program B has 56% arithmetic, 24% load, 11% branch, 9% store instructions.

c.       CPU X is the single-cycle CPU from class with a clock speed of 1.0 GHz.

d.      CPU Y is the multi-cycle CPU from class with a clock speed of 4.0 GHz.