EECE 527 - Advanced Computer Architecture

Spring 2011 (Jan 06, 2011 to Apr 07, 2011)
Thursdays 12:30 to 15:30 in MCLD 219

Description:

The microprocessor industry is undergoing a dramatic change with the widespread introduction of multicore processors. This course is about the numerous ways chip architects translate an ever growing supply of transistors into exciting products that take advantage of process technology improvements.

As semiconductor process technology changes, the tradeoffs underlying microprocessor design constantly evolve leading to dramatic changes in the design at the architecture and underlying microarchitecture level. In this course we study the major developments in microprocessor design over the past 10 to 15 years and then explore future directions for computer architecture in light of current process technology trends. The first part examines microarchitecture techniques employed in current superscalar processors from the unifying perspective of instruction flow, register and memory data flow. Then we explore the challenges to achieving the full benefits of future process technology scaling, the architecture and microarchitecture solutions currently being adopted, as well as potential solutions that may be adopted in the future.

The course should be of interest to most ECE graduate students, including hardware oriented students wishing to understand the impact of low level optimizations on system performance/cost; software oriented students interested in making the most effective use of future hardware systems; and communications or systems oriented students wishing to study examples of highly complex systems (with literally billions of interacting components).

Prerequisites:

A prior course in computer architecture is helpful but not essential. Familiarity with programming in C++, or a willingness to learn.

Course webpage:

Lecture material and announcements will be posted on Vista.

Topics:

A. Modern superscalar microarchitecture techniques:

1. Review of quantitative approaches, ISA design, caches, pipelining.
2. Superscalar organization: Instruction, register and memory dataflow techniques.
3. Advanced branch prediction and trace cache mechanisms.
4. Data capture versus non-data capturing scheduling windows.
5. Complexity effective superscalar design approaches and challenges.
6. Memory system design: hardware support for concurrent cache misses, dependence prediction and speculative bypassing.
7. Proposed value prediction mechanisms and their impact.
8. Hardware mechanisms for efficient multiprocessor memory consistency.
9. Prefetching techniques.
10. Detailed case study (e.g., Pentium Pro, Pentium 4, Opteron, etc...)

B. Advanced topics

1. Multithreading/multicore:
    • streaming processors, accelerator architectures (e.g., GeForce 8, IBM Cell (PS3), digital signal processors)
    • simultaneous multithreading and helper threads
    • cache sharing mechanisms (e.g., for providing fair access to on-chip resources)
    • on-chip interconnection networks and memory controllers
    • speculative multithreading and transactional memory
2. Techniques for analyzing/mitigating power, energy and temperature at the microarchitecture level
3. Impact of process variability on architecture, fault tolerant processor design

Instructor Information:

Name: Dr. Tor M. Aamodt
Email: aamodt@ece.ubc.ca
Office: KAIS 4043
Phone: 1.604.827.4116
Web: http://www.ece.ubc.ca/~aamodt

Textbook:

Readings will be based upon research papers. The following optional textbook makes a good reference:

Modern Processor Design: Fundamentals of Superscalar Processors,
John Paul Shen, Mikko H. Lipasti, McGraw Hill.

Assignments and Project:

There are two assignments which build up microarchitecture modeling skills. These assignments involve modifying an event driven simulator written in C++. The project may be either an exploration of a novel microarchitecture proposal or an evaluation of an existing proposal (typically this involves C/C++ programming, however in the past some students have used HDLs/FPGAs).

Grading:

20% Assignments
20% Paper reviews
10% Paper presentation (on a paper selected by the student)
50% Project