EECE 571b - Advanced Computer Microarchitecture

Spring 2008 (Jan 07, 2008 to Apr 11, 2008)
Thursdays 2:00 pm to 5:00 pm in FSC 1003

Description:

This is a course about how chip architects translate an ever growing supply of transistors into exciting products people want to buy.

As semiconductor process technology changes, the tradeoffs underlying microprocessor design evolve leading to dramatic changes in the underlying design at the microarchitecture level. In this course we first study the major developments in microprocessor microarchitecture design over the past 10 to 15 years and then explore potential future directions for microprocessor microarchitecture in light of current process technology trends. The first part examines the large number of existing techniques from the unifying perspective of instruction flow, register and memory data flow. This provides a basis for exploring current challenges and proposed solutions. See the detailed list of topics below.

The course will be of interest to: Communications or systems oriented students wishing to study examples of highly complex systems (some recent research has explored applications of QoS algorithms to improve memory system performance in microprocessors); hardware oriented students wishing to understand the impact of low level optimizations on system performance/cost; and software oriented graduate students interested in making the most effective use of future hardware systems.

Prerequisites:

A prior course in computer architecture is helpful but not essential. Familiarity with programming in C/C++ (or a willingness to learn).

Course webpage:

Lecture material and announcements will be posted on WebCT. (The first few lectures will also be posted at http://courses.ece.ubc.ca/571b/)

Topics:

A. Modern superscalar microarchitecture techniques:

1. Review of quantitative approaches, ISA design, caches, pipelining.
2. Superscalar organization: Instruction, register and memory dataflow techniques.
3. Advanced branch prediction and trace cache mechanisms.
4. Data capture versus non-data capturing scheduling windows.
5. Complexity effective superscalar design approaches and challenges.
6. Memory system design: hardware support for concurrent cache misses, dependence prediction and speculative bypassing.
7. Proposed value prediction mechanisms and their impact.
8. Hardware mechanisms for efficient multiprocessor memory consistency.
9. Prefetching techniques.
10. Detailed case study (e.g., Pentium Pro microarchitecture)

B. Current directions in research and industry

1. Multithreading/multicore:
    • streaming processors (e.g., GeForce 8, PS3 Cell, digital signal processors)
    • simultaneous multithreading and helper threads
    • cache sharing mechanisms
    • on-chip interconnection networks
    • speculative multithreading and transactional memory
2. Techniques for analyzing/mitigating power, energy and temperature at the microarchitecture level
3. Impact of process variability on architecture, fault tolerant processor design

Instructor Information:

Name: Dr. Tor M. Aamodt
Email: aamodt@ece.ubc.ca
Office: KAIS 4043
Phone: 1.604.827.4116
Web: http://www.ece.ubc.ca/~aamodt

Textbook:

Readings will be based upon research papers. The following textbook makes a good reference:

Modern Processor Design: Fundamentals of Superscalar Processors,
John Paul Shen, Mikko H. Lipasti, McGraw Hill.

Grading:

10% Paper reviews
10% Paper presentation (on a paper selected by the student)
25% Assignments
50% Project
5% Participation in group discussions on readings