EECE 578: Integrated Circuit Design-for-Test

[chip]Winter 2008

Instructor:         Dr. Andrι Ivanov

TA:                  TBD

Credits:            3

 

Sessions:

Tuesday: 14:00 - 17:00

Location: FSC 1221

 

 

Integrated Circuit Design-for-Test

 

 

This course addresses the issues, problems and solutions related to testing Very Large Scale Integrated (VLSI) Circuits and Systems on Chip (SoCs), as well as the design for testability of such circuits.    Topics include defect and fault modeling, test generation, logic and fault simulation, scan design, boundary scan, built-in self-test, memory testing, IDDQ testing, and core-based circuit testing. The emphasis is on digital circuit test, but some aspects of analog circuit testing are also treated in the course. Some advanced design issues as they relate to testing and testability are also addressed.  Students are assumed to have good previous IC design knowledge at all levels of abstraction from RTL to physical (layout) level.  Advanced state of the art topics in testing and DFT will be discussed, and the course involves a project in addition to homework exercises and reading assignments.