Links to videos from the 2017 offering of CPEN 211 can be found below, sorted by date (month-day refers to 2017). Slide set numbers are listed as "ssN". Slide numbers (pNN-MM) refer to the final version of slides (posted after lecture).
Lecture videos:
| Date + link to video | Slide Numbers | Topics |
| 09-07 | intro; ss1 p1-13 | Course introduction; What is Verilog? |
| 09-12 (*) | ss1 p14-55 | Verilog module syntax; effect of noise on analog and digital circuits; representing information. |
| 09-14 | ss1 p56-end; ss2 p4-16 | Combinational vs sequential logic; Boolean algebra; Equations to gates; NAND gates; Bubble rule. |
| 09-19 | flipped lecture #1 | Problem Set #1, Questions 6.2, 6.4, 6.12 |
| 09-20 | ss2 p2-3, 17-40 | Verilog for busses; module instantiation; Tutorial: Dally questions 6.12 and 3.16 |
| 09-21 | ss2 p41-71 | Module instantiation; one-hot; arbiter; module parameters; named association; testbenchs |
| 09-26 | ss2 p71-84; flipped lecture #2 | Debugging; Top-Level Module vs. I/O Pins; Always block; Q3 and Q4 from Problem Set 2 |
| 09-28 | ss2 p84-end; ss5 p1-27 | Rules for combinational logic always blocks; begin/else; Ambiguous else; FSMs in Verilog (1) |
| 10-03 | ss5 p27-end; ss6 p1-3 | Less error prone style for FSMs; Non-blocking assignments; Rules for purly synchronous always blocks. |
| 10-05 (*) | ss6 p3-20; Lab 5 intro | Combinational logic building blocks: Decoders, Encoders, One-hot select multiplexer; Lab 5 Introduction. Note: unfortunately, the built-in recording suffered the "no signal" issue (again). UBC Media, who operate the built-in recording system, will upload slides images synchronized to the video manually for the affected times "early" the week of Oct 10-13. Until they do, you will likely prefer to refer to Dave's backup recording. |
| 10-10 | ss6 p17-61 | One-hot select multiplexer, revisited; What's Inside an FPGA? Factoring (mux, encoder, decoder); Priority Encoder; Comparators |
| 10-12 | ss6 p61-99 | Magnitude comparator; Read-only memory; Hexadecimal; Addition in binary; 2's Complement |
| 10-17 | ss6 p99-end; ss7 p1-35 | 2's complement; subtractor; overflow; casex; datapath state mahines |
| 10-19 | ss7 p35-end; ss8 p1-3 | Designing arbitrary digital circuits; Read-write memories |
| 10-24 | ss8 p4-60 | CMOS Logic Gates; Standard Cell Design | 10-26 | flipped lecture #3 | ARM Assembly coding with ADD, SUB, LDR, STR; encoding ARM | 10-27 | recital session | Lab 7 walk through; Midterm walk through |
| 10-31 | flipped lecture #4 | ARM Assembly coding with branch instructions |
| 11-02 | ss8 p58-end; ss9 p1-60 | Complex Gates; Function Calls |
| 11-07 | ss9 p61-120 | Recursion; Local Variables; ASCII |
| 11-09 | ss9 p120-end; ss10 p1-25 | Pointers; Optimization; The Heap; Structs; Memory-Mapped I/O; Polling |
| 11-14 | ss10 p25-63 | Interrupt Service Routines: Timeline, Challenges, Implementation; Interrupts in ARM: Processor Modes, Vector Table, ISR Return |
| 11-16 | ss10 p64-end; ss11 p1-14 | Interrupt Service Routines: ARM's Generic Interrupt Controller, Multitasking; Error, Resolution, Accuracy, Fixed-Point |
| 11-21 | ss11 p14-end; ss12 p1-12 | Floating-point; Performance |
| 11-23 | ss12 p12-46; ss13 p17-21 | Processor Performance Equation, Five Stages, Structural and Data Hazards, Forwarding; Temporal and Spatial Locality (Caches) |
| 11-28 | ss12 p47-end; ss13 p1-42 | Control hazards; Memory technologies (Tape, Disk, SRAM, DRAM, Flash); Memory wall; Temporal locality; Data, Tag, Valid and Modified fields; Spatial locality; Cache blocks; Block offset |
| 11-30 | ss13 p43-72; ss14 p1-15 | Direct mapped and set-associative caches; Amdahl's Law |
(*) = pre-recorded
Other important videos for CPEN 211:
Videos w/o descriptions (updated automatically at end of lecture)
Lecture videos from 2016 (some content may change in 2017)
Quartus/ModelSim Installation Video
Submitting your lab from a laptop or home (using handin when not in MCLD112)
Lab 3-8 Debugging Video
Lab 5 Demonstration of using DE1-SoC with lab5_top.v
Lab 7 Stage 3 Demo using DE1-SoC