EECE 256 Digital Logic Design
Section 101/102 Term 1 - 2010/11
Final Exam in SRC A, 3:30-6:00, Tuesday Dec 7th
Midterm Solution & old final questions posted
Exam covers Chapters 1-8, excluding sections: 3.10, 4.12, 6.5*, 6.6, 7.8**, 8.9, 8.11-8.13.
* Counters with unused states are included.
** Basics of FPGAs (Blocks and CAD) are included.
Email: steveo at ece.ubc.ca
Review Class: TBA
Course Schedules (UBC course listings)
Lectures: Mon, Tue. Wed. Thu.; 13 :00 pm -14 :00 pm; McLeod 254
Tutorial (or Lecture): Fri. 13 :00 – 14 :00 pm; McLeod 254
Lectures: Mon, Tue. Wed. Thu.; 11 :00 am - 12 :00 noon; McLeod 228
Tutorial (or Lecture): Fri. 11 :00 am - 12 :00 noon; McLeod 228
Textbook: DIGITAL DESIGN, Moris Mano, Prentice Hall (4th Edition)
Solve, but do NOT hand in, all the homework problems, whether handed out or assigned in class. However, a quiz will be given during some of the tutorial sessions. Solutions will be posted after the quiz. Attend the tutorial for general questions and to find out how to solve the homework problems you had trouble with.
Final: 60%, one midterm: 25%, quizzes: 15%
MEETING/REVIEW: One to two days prior to final exam - will be announced, McLeod 228
* Note: There will be class at 11am/1pm as usual this day
FINAL EXAM: Dec 7, 3:30-6pm, Location SRC A
Non-Graphing Calculators Allowed. No Cheat Sheet.
CLASS NOTES (These will be updated throughout the term)
ASSIGNMENTS (These will be updated throughout the term)
(Q3, line 3 of truth table Next AB should be 01. Q2, last bit of line 1 should read X0, Q1, DA = AB’+A’Bx)
Schedule of Quizzes
Sept 17 - Tutorial
Oct 8 - Tutorial
Oct 25 - 5-7pm, Wood 2
These questions are good practice, but the questions from your text in chapters 1-8 are better as these were taken from a very old exam.
Marks to Date:
(Updated on Oct 26, 2010)