EECE 256 Digital Logic Design Section 101/102 Term 1 - 2010/11

Final Exam in SRC A, 3:30-6:00, Tuesday Dec 7^th Midterm Solution & old final questions posted Exam covers Chapters 1-8, excluding sections: 3.10, 4.12, 6.5*, 6.6, 7.8**, 8.9, 8.11-8.13. * Counters with unused states are included. ** Basics of FPGAs (Blocks and CAD) are included. Instructor:   Dr. Sidney Fels, Kaiser #4049   Steven Oldridge, MCLD 228 Email: steveo at ece.ubc.ca Office hours: Tuesday & Thursday 11:50 to 12:30pm and any other time by appointment Review Class: TBA Teaching Assistants: Elie H. Sarraf Di Xu Assem Bsoul Ehsan Nezhadarya Aaron Severance Course Schedules (UBC course listings) Section 101: Lectures: Mon, Tue. Wed. Thu.; 13 :00 pm -14 :00 pm; McLeod 254   Tutorial (or Lecture): Fri. 13 :00 – 14 :00 pm; McLeod 254 For the exact schedule of the integrated second year please check here   Section 102:   Lectures: Mon, Tue. Wed. Thu.;  11 :00 am - 12 :00 noon; McLeod 228   Tutorial (or Lecture): Fri. 11 :00 am - 12 :00 noon; McLeod 228 For the exact schedule of the integrated second year please check here Textbook: DIGITAL DESIGN, Moris Mano, Prentice Hall (4th Edition) Homework: Solve, but do NOT hand in, all the homework problems, whether handed out or assigned in class. However, a quiz will be given during some of the tutorial sessions. Solutions will be posted after the quiz. Attend the tutorial for general questions and to find out how to solve the homework problems you had trouble with. Grading: Final: 60%, one midterm: 25%, quizzes: 15% MEETING/REVIEW: One to two days prior to final exam - will be announced, McLeod 228 MIDTERM EXAM: Oct 25*, 5-7pm, WOOD2 BOTH SECTION * Note: There will be class at 11am/1pm as usual this day FINAL EXAM:  Dec 7,  3:30-6pm,  Location SRC A Non-Graphing Calculators Allowed. No Cheat Sheet. Topics Covered 1. History of Digital Computing 2. Digital Systems and Binary Numbers 3. Boolean Algrebra and Logic Gates 4. Gate-level Minimization 5. Combinatorial Logic 6. Synchronous Sequential Logic Design 7. Registers and Counters 8. Memory and Programmable Logic 9. Design using Different Digital Components 10. Some HDL approaches to Digital Design CLASS NOTES (These will be updated throughout the term) Class Notes Introduction Class Notes Set #1, Class Notes Set #2, Class Notes Set #3, Class Notes Set #4, Class Notes Set #5, http://www.falstad.com/circuit/e-index.html (scroll down to Sequential Logic) Class Notes Set #6, Class Notes Set #7, Class Notes Set #8, ASSIGNMENTS (These will be updated throughout the term) Assignment 1 Solutions for Assignment 1 (Q1, 2, 3, 5,6, 7) Solutons for Assignment 1 (Q4 and 8) Assignment 2 Solutions for Assignment 2 Assignment 3 Solutions for Assignment 3 Assignment 4 Solutions for Assignment 4 Assignment 5 Solutions for Assignment 5 (Q3, line 3 of truth table Next AB should be 01. Q2, last bit of line 1 should read X0, Q1, DA = AB’+A’Bx) Assignment 6 Solutions for Assignment 6 Assignment 7 Solutions for Assignment 7 Assignment 8 Solutions for Assignment 8  Schedule of Quizzes     Sept 17 - Tutorial     Sept 24 - Quiz 1 marks - section 101 marks - section 102           solutions 101 solutions 102 solutions     Oct 8 - Tutorial     Oct 15 - Quiz 2          marks - section 101           marks - section 102           solutions 101 solutions 102 solutions     Oct 25 - 5-7pm, Wood 2        sample midterms 2005 2006 2007 Midterm Solutions     Oct 29 - Tutorial     Nov 5 - Quiz 3 Solutions  (101, 102)   Nov 19 - Tutorial   Nov 26 - Quiz 4 Solutions (101, 102, Q4) Old final exam questions (from 1999 & 2000) These questions are good practice, but the questions from your text in chapters 1-8 are better as these were taken from a very old exam.  Marks to Date: marks - section 101 marks - section 102 (Updated on Oct 26, 2010)